Tag Archives: Hakodate

2023 Joint Convention, the Hokkaido Chapters of the Institutes of Electrical and Information Engineers

Mr. Chimkono, Mr. Kunii, Mr. Tanaka, and Mr. Saito presented their works at 2023 Joint Convention, the Hokkaido Chapters of the Institutes of Electrical and Information Engineers, which was held at Future University Hakodate on Oct 28th-28th.

  • Kenshiro Tanaka, Kota Hirai, Hiroshi Tsutsui, Takeo Ohgane, “A Feasibility Study on Power Consumption Reduction of IoT Device GPS Modules for Environmental Monitoring Systems and Its Prototype Evaluation,” Joint Conference of Electrical, Electronics and Information Engineers in Hokkaido, pp. 206-207, Oct. 2023 (in Japanese).
  • Yuki Saito, Kyotaro Kunii, Hiroshi Tsutsui, Takeo Ohgane, “An Investigation of Temporal Variations in LoRa Modulation-based Communication Performance,” Joint Conference of Electrical, Electronics and Information Engineers in Hokkaido, p. 208, Oct. 2023 (in Japanese).
  • Kyotaro Kunii, Hiroshi Tsutsui, Takeo Ohgane, “Investigating the Impact of LDPC Codes on LoRa Modulation Communication Performance,” Joint Conference of Electrical, Electronics and Information Engineers in Hokkaido, pp. 209-210, Oct. 2023 (in Japanese).
  • Aaron William Chimkono, Hiroshi Tsutsui, Takeo Ohgane, “Towards Robust Parking Classification in Snow: Training MobileNetV3 on a Custom Dataset,” Joint Conference of Electrical, Electronics and Information Engineers in Hokkaido, p. 254, Oct. 2023.

A student networking event was held during this convention. Students made presentations about their university, research activity, and student activity. Mr. Kunii who is the chair of IEEE Hokkaido University Student Branch introduced the activity of the student branch.

2017 Joint Convention, the Hokkaido Chapters of the Institutes of Electrical and Information Engineers

Mr. Watanabe presented his paper at 2017 Joint Convention, the Hokkaido Chapters of the Institutes of Electrical and Information Engineers, which was held at Future University Hakodate on Oct 28th-28th. In this paper, we presented an implementation approach to avoid memory conflicts of parallel processing to realize high throughput LDPC decoding.

  • Taishi Watanabe, Takahiro Ikeshita, Hiroshi Tsutsui, Takashi Imagawa, Yoshikazu Miyanaga, “A Design of High-Throughput LDPC Min-Sum Decoder Using Parallelization,” Joint Conference of Electrical, Electronics and Information Engineers in Hokkaido, pp. 102-103, Oct. 2017 (in Japanese).

A student exchange meeting was held during this convention. Students of each university made presentations about their university, research activity, and student activity. Mr. Watanabe who is the member of IEEE student branch at Hokkaido university introduced the activity of the student branch.