Mr. Watanabe presented his paper at 2017 Joint Convention, the Hokkaido Chapters of the Institutes of Electrical and Information Engineers, which was held at Future University Hakodate on Oct 28th-28th. In this paper, we presented an implementation approach to avoid memory conflicts of parallel processing to realize high throughput LDPC decoding.
- Taishi Watanabe, Takahiro Ikeshita, Hiroshi Tsutsui, Takashi Imagawa, Yoshikazu Miyanaga, “A Design of High-Throughput LDPC Min-Sum Decoder Using Parallelization,” Joint Conference of Electrical, Electronics and Information Engineers in Hokkaido, pp. 102-103, Oct. 2017 (in Japanese).
A student exchange meeting was held during this convention. Students of each university made presentations about their university, research activity, and student activity. Mr. Watanabe who is the member of IEEE student branch at Hokkaido university introduced the activity of the student branch.